1. Technical Field of the Invention
The present invention relates to memory circuits such as static random access memories and related methods.
2. Description of Related Art
As is known, integrated circuits are used in a wide variety of electronic equipment, including portable, or handheld, devices. Such handheld devices include personal digital assistants (PDA), CD players, MP3 players, DVD players, AM/FM radio, a pager, cellular telephones, computer memory extension (commonly referred to as a thumb drive), etc. Each of these handheld devices includes one or more integrated circuits to provide the functionality of the device. As an example, a handheld FM radio receiver may include multiple integrated circuits to support the reception and processing of broadcast radio signals in order to produce an audio output that is delivered to the user through speakers, headphones or the like. Many such integrated circuits include a processing device that executes a program that includes a sequence of instructions that are stored in a memory device such as a random access memory (RAM). These devices are typically powered from a small battery that has a limited capacity. Reduced power consumption is an important consideration for these devices in order to increase the amount of time the device can operate before the battery needs to be recharged or replaced.
FIG. 1 presents a schematic block diagram representation of a prior art RAM 240. In particular, a static RAM (SRAM) configuration is disclosed that includes an array of individual memory cells such as memory cell 206, that store binary values and that are arranged in a row and column format for ease in binary addressing. A particular memory cell, such as memory cell 206, is accessed by decoding the address 210 with row decoder 200 and column decoder 202. Row decoder 200 selects the particular wordline 212 that corresponds to the row of memory cells that contains memory cell 206. Column decoder 202 selects the particular complementary bitlines 214 and 216, driven by bitline conditioner 204, that correspond to the column of memory cells that contains memory cell 206. Column multiplexer (MUX) 208 couples the selected bitlines 214 and 216 to sense amplifier 224 and data buffer 226. Data are written to individual memory cells from data in line 222 and data buffer 226. Data are read from individual memory cells by sense amplifier 224 and are output on data out line 220.
FIG. 2 presents a graphical representation of the voltage of complementary bitlines 214 and 216 in response to a read operation. During a read operation, bit conditioner 204 precharges the bitlines 214 and 216 to a “high” voltage state. Wordline 212, corresponding to the row of memory cells that contains memory cell 206, is pulsed high, causing the voltage on one of the bitlines 214 or 216 to fall (depending on whether a 1 or 0 is currently stored in memory cell 206), due to a current discharge through memory cell 206. At time t1, the voltage difference between bitlines 214 and 216 reaches a magnitude Δ. The sense amplifier 224 is connected to the bitlines 214 and 216 through column MUX 208 (as selected by column decoder 202 and column enable signal 218). Sense amplifier 224 converts this voltage difference to a 1 or 0 based on the polarity of the difference. After the data from memory cell 206 is read, bitline conditioner 204 precharges the bitlines 214 and 216 back to the high voltage state from times t2 to t3 by supplying a replenishment current to bitline 214.
While the activities above are occurring in memory cell 206, similar events are occurring in each of the other memory cells (not specifically shown) in the row served by wordline 212. When wordline 212 is pulsed high, the voltage on one of the bitlines corresponding to the other memory cells begins to fall (depending on whether a 1 or 0 is currently stored in the memory cell). At time t1, the voltage difference between the bitlines reaches a magnitude Δ. The corresponding bitline conditioners precharge the bitlines back to the high voltage state from times t2 to t3 by supplying a replenishment current to the other bitlines. The sense amplifier 224 remains disconnected from the bitlines of these other memory cells because column MUX 208 has selected bitlines 214 and 216. While all the bitlines associated with memory cells addressed by wordline 212 generate a voltage delta, only the bitlines selected by column MUX 208 are actually used. The other memory cells in the selected row are therefore, by design, are not involved in the data read operation. However, the other bitlines consume additional power during the read operation due to the current discharge and corresponding current replenishment to precharge the bitlines of these other memory cells back to a high voltage state.
One method of reducing the amount of power consumed by the memory device involves shortening the discharge cycle by reducing pulse width of wordline 212 and thereby reducing time t1, and the voltage difference Δ. While this configuration creates less bitline swing and requires less replenishment current, it requires more accurate sense amplifier timing, greater bitline stability, and overall, makes the memory more susceptible to noise and variations of supply voltage, temperature and device characteristics.
The need exists for memory devices that consume less power and that can be implemented efficiently in integrated circuit designs.